Several circuit systems in an integrated circuit (IC) chip use clocks (or clock signals) that have large divide ratios (e.g., divide ratio ranging from 2 to 64), and these divided clocks are generated from a source clock. These various circuit systems are generally tested at their functional clock frequencies (also referred to as at-speed test) to determine proper function of operation. One such set of circuits are transceiver digital signal processing filters that apply clocks generated by one or more clock generators, and these clocks are used by these filters to transmit or receive radio messages. Current solutions for at-speed scan capture are rigid in a sense that they can only be plugged in at a clock source and then generate a fixed number of divided and derived clocks for at-speed scan capture phase. Testing coverage of these various circuits is a challenge because the current at-speed testing architecture cannot handle data transfer between circuit paths clocked or sampled by clocks generated using different divide ratios (e.g., clocks with divide ratios of 16 and 64).